1. Field of the Invention
The present invention relates to an integrated multilayer chip capacitor module and an integrated circuit apparatus having the capacitor module, and more particularly, an integrated multilayer chip capacitor module which has capacitors mounted at a higher density to reduce power network impedance in high and low frequency regions, and a micro-processor unit (MPU) integrated circuit apparatus having the same.
2. Description of the Related Art
In general, a multilayer chip capacitor has internal electrodes of different polarities deposited alternately to interpose each of dielectric layers. This multilayer chip capacitor advantageously ensures a smaller size, a higher capacity and easy mountability, thus widely used as a capacitive component of various electronic devices. Especially, the multilayer chip capacitor is considerably utilized as a decoupling capacitor for stabilizing a high frequency power circuit for use in e.g., a micro-processor unit (MPU). To be employed as a decoupling capacitor of the MPU, the capacitor should have a low ESL. This demand for a lower ESL has been rising due to a higher speed of the MPU and a resultant higher current and lower voltage trend.
To be employed in an MPU package, decoupling capacitors need to be connected in parallel to lower power network impedance. For much lower impedance, a greater number of capacitors are connected in parallel. However, a greater number of capacitors connected in parallel increase a total mounting area, thereby resulting in less decline in overall impedance in a limited mounting area.
To overcome problems associated with a limited mounting area, the capacitors may be reduced in size so that a greater number of capacitors can be mounted in the MPU package, with an overall mounting area maintained. The smaller-sized capacitors may decrease total impedance at a high frequency, but increase impendence at a low frequency due to decrease in total capacitance. This is because impedance at a high frequency is mainly determined by ωL, where ω denotes an angular frequency, and L denotes an inductance, whereas impedance at a low frequency is largely determined by 1/ωC, where C is capacitance.
Therefore to reduce power network impedance at a high frequency and a low frequency, it is necessary that individual capacitors be reduced in ESL and the decoupling capacitors be mounted at a higher density. That is, the multilayer chip capacitors should be arranged to ensure as large capacitance as possible in a limited overall mounting area, and respective multilayer chip capacitors should be low in ESL.
An integrated capacitor assembly (module) having a plurality of multilayer chip capacitors arrayed thereon to be connected with one another has been proposed. FIG. 1 is a perspective view illustrating a conventional integrated multilayer capacitor module. Referring to FIG. 1, the integrated multilayer capacitor module 10 includes a plurality of two-terminal multilayer chip capacitors 11 and a capacitor support 15 accommodating the capacitors. Each of the capacitors 11 has two external electrodes 12 formed at both sides thereof, respectively. The capacitors 11 are separated from one another by side walls 15a and disposed in the capacitor support. A module or assembly of these integrated capacitors may be mounted on a circuit board, e.g., micro-processor unit (MPU) package.
In the multilayer chip capacitor module of FIG. 1, ‘two terminal’ capacitors can be integrated into a single module structure, but ‘multi-terminal’ multi-layer capacitors cannot be mounted at a higher density and with lower ESL. To further reduce impedance at a high and low frequency, multi-terminal low-ESL multilayer chip capacitors for use in the MPU package should be mounted at a higher density.